Following this rationale, in this paper we introduce for the
first time to our knowledge the concept of WDM into optical
RAM architectures in view of presenting a complete 4-cell all
optical memory row with WDM capabilities, as a combination
of a multi-wavelength Access Gate (AG) and 4 RAM cells [14],
[19]. The proposed WDM RAM architecture allows processing
of a WDM-formatted 4-bit word with the use of one AG per
RAM row, thus increasing the RAM bank scalability while significantly
relaxing the requirements in terms of active components
and power consumption. The scheme is shown to support
a 10 Gbit/s line-rate operation for the incoming 4-bit data word
streams, with a power consumption of 15 mW/Gbit/s for the
WDM-AG and 120 mW/Gbit/s for the AOFFs leading to a total
power consumption of 495 mW/Gbit/s per RAM row. A similar
electronic 4-bit RAM row comprising state-of-the-art s-RAM
cells exhibits 440 mW/Gb/s and 232 mW/Gb/s (during the Read
and Write operation, respectively [25].
The rest of the paper is organized as follows: Section II describes
the concept of the proposed 4 4 WDM optical RAM
bank and Section III presents the first fundamental building
block, the multi-wavelength Access Gate that enables the efficient
control of 4 RAM cells. Section IV presents the second
fundamental building block, the dual-wavelength bit input
RAM cell architecture that can be combined with the WDM
AG in order to process WDM-formatted words into an optical
RAM row architecture. Section V discusses the perspective of
including wavelength dimension in optical RAM architectures
and addresses the issues of re-configurability in optical cache
mapping schemes.
mapping schemes.