A. Niagara2 Architecture
Fig. 2 shows the Niagara2 block diagram, and Fig. 3 shows
the die micrograph. The chip has eight SPARC Cores, a 4 MB
shared Level2 cache, and supports concurrent execution of
64 threads. The Level2 cache is divided into eight banks of
512 kB each. The SPARC Cores communicate with the Level2
cache banks through a high bandwidth crossbar. Niagara2 has
a 8 PCI-Express channel, two 10 Gb Ethernet ports with
XAUI interfaces and four memory controllers each controlling