to RAM S0 as the variable node index. In the second round,
comparisons are carried out on the messages stored in RAM S0
and the v-to-c messages of the second variable node to find the
messages with the smallest nonzero LLRs. The comparison
output vector is written into RAM S1. Since the entries in
each v-to-c message vector are stored in the order of increasing
LLR, the comparison can start with the first nonzero-LLR entries
in the two input vectors. If the LLR fromRAMS0 is smaller, the
corresponding entry will be stored intoRAMS1. In addition, the
next entry ofRAMS0 will be read out and sent to the comparator
in the next clock cycle. Otherwise, the v-to-c message is stored
into RAM S1 together with the current variable node index.
Similarly, the next entry in the v-to-c message vector will be read
out and sent to the comparator in the next clock cycle. Such comparisons
will be repeated until entries are derived for the
output vector. In each of the third and later rounds, comparisons
are carried out on the output vector from the previous round and
the v-to-c message vector of another variable node.RAMS0 and
S1 are used in a ping-pong manner to store comparison input and
output vectors. Since entries are kept in the output vector,
clock cycles are required for the comparisons in each
of the second and later rounds of the sorting. In addition, one
clock cycle is spent on reading the zero-LLR entry from the
v-to-c message RAM in each round. Hence the sorting takes
clock cycles.