The L1 cache is divided into two 16 KB segments—one for data and the other for instructions. The L2 cache is 96 KB and holds both instructions and data. L1 data cache contents are swapped automatically with the L2 cache as needed. The instruction fetch and branch prediction unit examines incoming instructions for conditional branches and attempts to prefetch instructions from both branch paths into the L1 instruction cache. The branch prediction unit also interacts with the CPU execution units to determine the likelihood of branch conditions being true or false.