has a modified copy of the line. The initiating processor surrenders the bus and
waits. The other processor gains access to the bus, writes the modified cache line
back to main memory, and transitions the state of the cache line to invalid (because
the initiating processor is going to modify this line). Subsequently, the initiating
processor will again issue a signal to the bus of RWITM and then read the line
from main memory, modify the line in the cache, and mark the line in the modified
state.
The second scenario is that no other cache has a modified copy of the requested
line. In this case, no signal is returned, and the initiating processor proceeds to read in
the line and modify it. Meanwhile, if one or more caches have a clean copy of the line
in the shared state, each cache invalidates its copy of the line, and if one cache has a
clean copy of the line in the exclusive state, it invalidates its copy of the line.