At the next rising edge, the outputs from A are fixed (resulting in fixed outputs from device B) and these outputs are latched in device A. It should be clear that one fundamental requirement for logic such as this to function properly is that all asynchronous devices must be able to transition their outputs transitively in less than one–half clock cycle time. In other words, the inputs to a synchronous device must be stable and unchanging at the rising edge transition. As long as any output changes from synchronous devices(during falling edge)are propagated through the asynchronous devices during the “zero” clock period, the logic works as expected.