AMD-K6®-2 Processor Block Diagram. As shown in Figure 1 on page 7, the high-performance, out-of-order execution engine of the AMD-K6-2 processor is mated to a split level-one 64-Kbyte writeback cache with 32 Kbytes of instruction cache and 32 Kbytes of data cache. The instruction cache feeds the decoders and, in turn, the decoders feed the scheduler. The ICU issues and retires RISC86 operations contained in the scheduler. The system bus interface is an industry-standard 64-bit Super7 and Socket 7 demultiplexed bus.
The AMD-K6-2 processor combines the latest in processor microarchitecture to provide the highest x86 performance for
today’s personal computers. The AMD-K6-2 processor offers true sixth-generation performance and x86 binary software
compatibility