A split shared-bus architecture with multiple si-
multaneous bus accesses is proposed. Compared to traditional
bus architectures, the performance of proposed architecture is
higher because of the ability to deliver multiple bus transactions
in one bus cycle. We also propose an implementation of the ar-
biter, which not only detects and grants multiple compatible bus
transactions, but also controls splitters properly to establish the
communication paths for those transactions. Experimental re-
sults show that the bus architecture can have up to 2.3 times im-
provement in the effective bandwidth and up to 5 times reduction
in the communication latency. Moreover, the arbiter implemen-
tation has reasonable area and timing cost, making it suitable for
high performance SoC applications.