B. Computation Scheduling
Taking a QCNB-LDPC code whose matrix has three
layers as an example, the scheduling of the computations in
the decoding process is illustrated in Fig. 6. For the sorters
and path constructors, the two digits on a bar denote that
the hardware unit is occupied by the computations for layer
in iteration for that period of time. For RAM E blocks,
means that the memory block is used to store the sorted
v-to-c messages derived for layer in iteration . In addition,
if there is “PC I” or “PC II” on a bar, it represents that the Path
Constructor I or II is reading from that memory block. During
the sorting for each layer, the two shaded RAM E blocks are
used in a ping-pong manner for storing intermediate results.
The absence of bars translates to that the computation unit or
memory is not required for any computation or data storage
during that time.
B. Computation Scheduling
Taking a QCNB-LDPC code whose matrix has three
layers as an example, the scheduling of the computations in
the decoding process is illustrated in Fig. 6. For the sorters
and path constructors, the two digits on a bar denote that
the hardware unit is occupied by the computations for layer
in iteration for that period of time. For RAM E blocks,
means that the memory block is used to store the sorted
v-to-c messages derived for layer in iteration . In addition,
if there is “PC I” or “PC II” on a bar, it represents that the Path
Constructor I or II is reading from that memory block. During
the sorting for each layer, the two shaded RAM E blocks are
used in a ping-pong manner for storing intermediate results.
The absence of bars translates to that the computation unit or
memory is not required for any computation or data storage
during that time.
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