The Cortex-M3 core architecture consists of a 32-bit processor (CM3)
with a small set of key peripherals – a simplified version of this core is illustrated
in Figure 2.2. The CM3 core has a Harvard architecture meaning that
it uses separate interfaces to fetch instructions (Inst) and (Data). This helps
ensure the processor is not memory starved as it permits accessing data and
instruction memories simultaneously. From the perspective of the CM3, everything
looks like memory – it only differentiates between instruction fetches
and data accesses. The interface between the Cortex-M3 and manufacturer