Our baseline configuration is explained in detail in Section 5.1. To compare the same area as our heterogeneous-cell designs, we increase the cache capacity in the L1 and L2 caches by 25%, and the L3 cache by 12.5%. We use a 40KB, 10-way L1 data cache, a 320KB, 10-way L2 cache, and an 18-way, 4.5 MB L3 cache. This configuration could not operate