A split shared-bus architecture with multiple simultaneous bus accesses is proposed. Compared to traditional
bus architectures, the performance of proposed architecture is
higher because of the ability to deliver multiple bus transactions
in one bus cycle. We also propose an implementation of the arbiter, which not only detects and grants multiple compatible bus
transactions, but also controls splitters properly to establish the communication paths for those transactions. Experimental results show that the bus architecture can have up to 2.3 times improvement in the effective bandwidth and up to 5 times reduction in the communication latency. Moreover, the arbiter implementation has reasonable area and timing cost, making it suitable for
high performance SoC applications.