In the proposed set-up shown in Fig. 1, the FPGA-based design serves as a shortest-path computation unit (SPCU), whose services are utilised by a host system when necessary. The connectivity information of the input graph is represented in the form of links in the host system’s memory in any random order. Data corresponding to each link consists of the index of the start node, the index of the end node and the weight of the link. Since the SPCU serves