Since the three gridded clocks, l2clk, drl2clk, and iol2clk, are
ultimately derived from the same reference, they are ratioed syn-
chronous. However, only l2clk
–
drl2clk and iol2clk-l2clk cross-
ings need to be addressed. The known periodic relationships of
the two interfaces are exploited to perform simpli
fi
ed domain
crossing, described next. Before proceeding, it is necessary to
make a distinction between clocks at the destination (suf
fi
xed
by l2clk) and those at the source (pre
fi
xed by pll_) in Fig. 12
and Fig. 14; as shown in Fig. 12, the latency may vary between
half to one and a half CMP cycles.