Even though we do not know the initial state (the ? for q1 and q2), the 0
input forces the system to state 00 at the next clock time and we can complete
the trace. Note that the output is known for two clock periods after
the input is not, since the system cannot reach state 10 (the only state for
which there is a 1 output) any sooner than that. A word of caution: The
present state and the present input determine the present output and the
next state, as indicated.
The timing diagram for this example is shown in Figure 6.29. It
illustrates a peculiarity of Mealy systems.* Note that there is a false output
(sometimes referred to as a glitch), that is, the output goes to 1 for a
short period even though that is not indicated in the timing trace nor in
the state table.