The linear address on the IA-32 is 32 bits long and is formed as follows.
The segment register points to the appropriate entry in the LDT or GDT.
The base and limit information about the segment in question is used to generate a linear address. First, the limit is used to check for address validity.
If the address is not valid, a memory fault is generated, resulting in a trap to the operating system. If it is valid,
then the value of the offset is added to the value of the base, resulting in a 32-bit linear address.
This is shown in Figure 8.22. In the following section, we discuss how the paging unit turns this linear address into a physical address.