II. PROBLEM
DESCRIPTION
In
the multiprocessor architecture shared memories are
support to establishing the communication between the
Processors
. Individual processors are having its own memory
due to that executes each task without inter depen
d
encies. The
multi UART performs seria
l commun
i
cation using FIFO [2]
technique. This also introduces errors in transactions of data
and delay.
Consider the following code:
Integ_temp= temp_1;
temp_1= temp_1+1;
In multiprocessor environment P_1 and P_2 are designated as
two different proces
sors may use the above code there is a
possibility of number of outcomes