Data level parallel (DLP) can be accomplished conveniently by taking advantage of coherent operations.
But when execution units operate on data with same actions simultaneously, “Peak-Bottom” may arouse if concerning storage accessing.
That is to say, because of identical movements, executing unit may access data from memory at one cycle which pressing the bandwidth of processor and considered as “peak”, or no one uses memory at all in other cycles which wasting the bandwidth and considered as “bottom”.
All of these conveniences and challenges should be discussed when constructing specific processor structure.