are used. Rather than containing PALs, FPGAs have as their basic building block a general purpose logic generator (typically three to five variables), with multiplexers and a flip flop. These blocks are connected by a programmable routing network, which also connects to input/output blocks. The logic generator is effectively a lookup table (LUT), often with a flip flop. A three-variable LUT is shown in Figure 8.14, with a flip flop that may be bypassed if Control is 0. Each cell can be programmed to a 0 or a 1; thus, any three-variable function can be created.