We should note that in this simulation approach, we do not take into account either the speed–of–light delays on the wires or the rise–time delays for the various devices in the design. For simulations that need this level of detail, a gate–level simulation would certainly be the method of choice. Here, we assume that all asynchronous devices will transitively produce stable outputs in less than one half of a clock period. Interestingly, our approach resulted in a discrete event simulation without the need for a sorted pending event list! Rather, we simply maintained a scalar list of all devices using clock inputs, and called the Rising Edge method on each, followed by a call to the Falling Edge method on each,and of course repeating this process infinitely. In no cases did any of the clock tick calls result in any future events!