An oxide thickness of 3 nm is needed for
CMOS transistors with channel lengths of 100nm orless [7].
This thickness comprises only a few layers of atoms and is
approaching fundamental limits which is around 1to 1.5 nm
[8]. The thin oxide layer is subject to quantum-mechanical
tunneling, giving rise to a gatele akage current that increases
exponentially as the oxide thickness is scaled down. This
tunneling current can initiate a damage leading to the fallible
of the dielectric[9]