a b s t r a c t
Ultrathin silicon based solar cells provide a viable way to reduce the material usage and diversify their
applications. However, complex light-trapping structures are always needed to be fabricated to enhance
light absorption, which will lead to exacerbation of carrier collection and expensive fabrication cost. Here,
we report very simple planar flexible crystalline silicon-polymer hybrid solar cell with thickness about
18 m, whose power conversion efficiency (PCE) reaches 5.68%. By introducing the amorphous silicon
layer to passivate the Silicon/Polymer interface in our device, with accuracy control of the thickness of
2 nm to balance the passivation effect and the deterioration of internal electric field, the short current
density reaches 83.0% of the theoretical limit. Additionally, we found that the average PCE of solar cells
passivated by such technology is 5.8% and 7.1% enhanced compared with those without passivation (Hterminated)
and passivated by native oxide approaches. The simple device structure provided in this
study has great practicability, and the passivation processes can be duplicated for other silicon based
photovoltaic devices.
© 2016 Elsevier B.V. All rights reserved.
1. Introduction
Ultrathin solar cells provide an effective way of reducing material
usage, utilizing low quality material and realizing diverse like
flexible applications [1–3]. Along with fabrication techniques for
ultrathin crystalline silicon (c-Si) wafer that have advanced to a
level where desired thickness, roughness and composition can be
readily synthesized by etching and other techniques [4–6], ultrathin
c-Si based solar cells especially the c-Si/polymer hybrid ones
have attracted a lot of attention [7–12]. This is because such cSi/polymer
solar cell is much suitable to realize low temperature
and large area fabrication as it does not require a complex junction
fabrication process and it usually has simple structures [13,14].
It has been reported that the power conversion efficiency (PCE)
of ultrathin c-Si/PEDOT:PSS device has reached 6.6% [13]. Where
Sharma et al have made great efforts in fabricating light-trapping
structures, including silicon pillars on the front-surface and silver
particles on the back-surface, to enhance light absorption. Indeed,
the photocurrent density of devices having these structures is dramatically
enhanced. However, these complex architectures have
also brought about abundant energy losses (carrier recombination)
∗ Corresponding author. Tel./fax: +86 1061772951.
E-mail address: mcli@ncepu.edu.cn (M. Li).
due to the increased interface defects. Such increased energy losses
can be reflected by the fact that, the ratio of the measured photocurrent
density to the theoretical limit (R-M/T) for device with
light-trapping architectures (51%, 18.50 to 36.51 mAcm2) is much
lower than that of device withoutlight-trapping architectures (76%,
15.06 to 19.94 mAcm2) [13]. Additionally, the light-trapping structures
also complicate the fabrication process thus increasing the
cost, and as a result it is difficult to ensure the process consistency.
From the above considerations, planar ultrathin solar cells are more
suitable for practical application.
In this work, we fabricate simple planar c-Si/PEDOT:PSS solar
cell of about 18 m thickness, which has good flexibility. Focusing
on reducing the carrier recombination, two passivation technologies
have been carried out. The two passivation technologies are
native oxidizing and depositing intrinsic amorphous silicon (i a-Si)
on the silicon at the c-Si/PEDOT:PSS interface. The depositing of
i-a-Si layer is the best method, and by controlling its thickness to
2 nm the PCE of device can reach 5.68% with R-M/T about 83.0%.
2. Experiments
2.1. Fabrication of ultrathin silicon
originally, the n-type (1 0 0), double side-polished, 4-in. silicon
wafers (resistivity, 1–5 cm) with a thickness of 500 ± 10 m were
http://dx.doi.org/10.1016/j.apsusc.2016.01.129
0169-4332/© 2016 Elsevier B.V. All rights reserved.
Y. Li et al. / Applied Surface Science 366 (2016) 494–498 495
ultrasonically cleaned in acetone, ethanol and deionized water for
10 min, respectively. Subsequently,the substrates were rinsed with
deionized (DI) water and dried with a nitrogen gun. After that, the
clean silicon wafers were immersed in KOH solution with concentration
of 50 wt.% at 90 ◦C for certain duration of time, to obtain
18 m free-standing c-Si membranes.
2.2. Silicon passivation
the ultrathin c-Si wafer is first cleaned by deionized (DI) water.
The samples without passivation were treated by immersing the
silicon wafer into HF solution (V:V= 1:2) at room temperature for
2 min;the native oxide method was done by placing the HF-cleaned
wafer in a dry dish with air condition; and the amorphous silicon
passivation was carried out by depositing i a-Si layer on the HFcleaned
silicon wafer using the PECVD equipment for 20s at 250 ◦C.
In the i a-Si deposition process, a 165 sccm mix
a b s t r a c tUltrathin silicon based solar cells provide a viable way to reduce the material usage and diversify theirapplications. However, complex light-trapping structures are always needed to be fabricated to enhancelight absorption, which will lead to exacerbation of carrier collection and expensive fabrication cost. Here,we report very simple planar flexible crystalline silicon-polymer hybrid solar cell with thickness about18 m, whose power conversion efficiency (PCE) reaches 5.68%. By introducing the amorphous siliconlayer to passivate the Silicon/Polymer interface in our device, with accuracy control of the thickness of2 nm to balance the passivation effect and the deterioration of internal electric field, the short currentdensity reaches 83.0% of the theoretical limit. Additionally, we found that the average PCE of solar cellspassivated by such technology is 5.8% and 7.1% enhanced compared with those without passivation (Hterminated)and passivated by native oxide approaches. The simple device structure provided in thisstudy has great practicability, and the passivation processes can be duplicated for other silicon basedphotovoltaic devices.© 2016 Elsevier B.V. All rights reserved.1. IntroductionUltrathin solar cells provide an effective way of reducing materialusage, utilizing low quality material and realizing diverse likeflexible applications [1–3]. Along with fabrication techniques forultrathin crystalline silicon (c-Si) wafer that have advanced to a
level where desired thickness, roughness and composition can be
readily synthesized by etching and other techniques [4–6], ultrathin
c-Si based solar cells especially the c-Si/polymer hybrid ones
have attracted a lot of attention [7–12]. This is because such cSi/polymer
solar cell is much suitable to realize low temperature
and large area fabrication as it does not require a complex junction
fabrication process and it usually has simple structures [13,14].
It has been reported that the power conversion efficiency (PCE)
of ultrathin c-Si/PEDOT:PSS device has reached 6.6% [13]. Where
Sharma et al have made great efforts in fabricating light-trapping
structures, including silicon pillars on the front-surface and silver
particles on the back-surface, to enhance light absorption. Indeed,
the photocurrent density of devices having these structures is dramatically
enhanced. However, these complex architectures have
also brought about abundant energy losses (carrier recombination)
∗ Corresponding author. Tel./fax: +86 1061772951.
E-mail address: mcli@ncepu.edu.cn (M. Li).
due to the increased interface defects. Such increased energy losses
can be reflected by the fact that, the ratio of the measured photocurrent
density to the theoretical limit (R-M/T) for device with
light-trapping architectures (51%, 18.50 to 36.51 mAcm2) is much
lower than that of device withoutlight-trapping architectures (76%,
15.06 to 19.94 mAcm2) [13]. Additionally, the light-trapping structures
also complicate the fabrication process thus increasing the
cost, and as a result it is difficult to ensure the process consistency.
From the above considerations, planar ultrathin solar cells are more
suitable for practical application.
In this work, we fabricate simple planar c-Si/PEDOT:PSS solar
cell of about 18 m thickness, which has good flexibility. Focusing
on reducing the carrier recombination, two passivation technologies
have been carried out. The two passivation technologies are
native oxidizing and depositing intrinsic amorphous silicon (i a-Si)
on the silicon at the c-Si/PEDOT:PSS interface. The depositing of
i-a-Si layer is the best method, and by controlling its thickness to
2 nm the PCE of device can reach 5.68% with R-M/T about 83.0%.
2. Experiments
2.1. Fabrication of ultrathin silicon
originally, the n-type (1 0 0), double side-polished, 4-in. silicon
wafers (resistivity, 1–5 cm) with a thickness of 500 ± 10 m were
http://dx.doi.org/10.1016/j.apsusc.2016.01.129
0169-4332/© 2016 Elsevier B.V. All rights reserved.
Y. Li et al. / Applied Surface Science 366 (2016) 494–498 495
ultrasonically cleaned in acetone, ethanol and deionized water for
10 min, respectively. Subsequently,the substrates were rinsed with
deionized (DI) water and dried with a nitrogen gun. After that, the
clean silicon wafers were immersed in KOH solution with concentration
of 50 wt.% at 90 ◦C for certain duration of time, to obtain
18 m free-standing c-Si membranes.
2.2. Silicon passivation
the ultrathin c-Si wafer is first cleaned by deionized (DI) water.
The samples without passivation were treated by immersing the
silicon wafer into HF solution (V:V= 1:2) at room temperature for
2 min;the native oxide method was done by placing the HF-cleaned
wafer in a dry dish with air condition; and the amorphous silicon
passivation was carried out by depositing i a-Si layer on the HFcleaned
silicon wafer using the PECVD equipment for 20s at 250 ◦C.
In the i a-Si deposition process, a 165 sccm mix
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