I
2
C is appropriate for interfacing to devices on a single board, and can be
stretched across multiple boards inside a closed system. An example is a host CPU on a
main embedded board using I2C to communicate with user interface devices located on a
separate front panel board. I2C is a two-wire serial bus, as shown in Figure 1. There's no
need for chip select or arbitration logic, making it cheap and simple to implement in
hardware. The two I2C signals are serial data and serial clock. Together, these signals
make it possible to support serial transmission of 8-bit bytes of data-7-bit device
addresses plus control bits-over the two-wire serial bus.
In a bind, an I2C slave can hold off the master in the middle of a transaction using what's
called clock stretching (the slave keeps SCL pulled low until it's ready to continue). Most
The I2C protocol can also support multiple masters. There may be one or more slaves on
the bus. Both masters and slaves can receive and transmit data bytes.
Each I2C-compatible hardware slave device comes with a predefined device address, the
lower bits of which may be configurable at the board level. The master transmits the
device address of the intended slave at the beginning of every transaction. Each slave is
responsible for monitoring the bus and responding only to its own address. This
addressing scheme limits the number of identical slave devices that can exist on an I2C n.