Processing elements are arranged in accordance with tile computing paradigm into bi-directional mesh of 8 × 8 processing elements across the whole chip, forming processing array (PA). Each PE integrates activation frames store as the storage of activation frames, arithmetic and logic unit for instructions execution and control unit. All PEs are unified general purpose computing units with simple design as well as I/O elements which are also simple and unified units.
Input/Output (IO) elements connected to the pins of the chip are localized at the edges of processing array. I/Os are used not only for communication with surrounding equipment of computer, but also allow creation of multi- chip computer architectures, where I/Os on different
chips are creating bridges between processing elements of
different processing arrays