2-cycle latency. Addresses can be hashed to distribute accesses
across different sets in case of hot cache sets caused by refer-
ence con
fl
icts. All arrays are protected by single error correc-
tion, double error detection ECC, and parity. Data from different
ways and different words is interleaved to improve soft error
rates.
The L2 cache used a unique row-redundancy scheme. It is im-
plemented at the 32 kB level and is illustrated in Fig. 9. Spare
rows for one array are located in the adjacent array as opposed to
the same array. In other words, spare rows for the top array are
located in the bottom array and vice versa. When redundancy is
enabled, the incoming address is compared with the address of
the defective row and if it matches, the adjacent array (which is
normally not enabled) is enabled to read from or write into the
spare row. Using this kind of scheme enables a large (
30%)
reduction in X-decoder area. The area reduction is achieved be-
cause the multiplexing required in the X-decoder to bypass the
defective row/rows in the traditional row redundancy scheme is
no longer needed in this scheme.