If the OSCCLK input signal is missing, then the PLL will output a default limp mode frequency and the
VCOCLK counter will continue to increment. Since the OSCCLK signal is missing, the OSCCLK counter
will not increment and, therefore, the VCOCLK counter is not periodically cleared. Eventually, the
VCOCLK counter overflows and, if required, the device switches the CLKIN input to the CPU to the limp
mode output frequency of the PLL.
When the VCOCLK counter overflows, the missing clock detection logic resets the CPU, peripherals, and
other device logic. The reset generated is known as a missing clock detect logic reset (MCLKRS). The
MCLKRS is an internal reset only. The external XRS pin of the device is not pulled low by MCLKRS and
the PLLCR and PLLSTS registers are not reset.
In addition to resetting the device, the missing oscillator logic sets the PLLSTS[MCLKSTS] register bit.
When the MCLKCSTS bit is 1, this indicates that the missing oscillator detect logic reset the part and that
the CPU is now running either at or one-half of the limp mode frequency.