stores the messages for the next block column of computed
by the previous decoder unit. Such buffering is necessary since
the messages are not read out one in each clock cycle by the
sorters as discussed previously.
During the sorting process, two RAM E blocks are used in a
ping-pong manner as the RAM S0 and RAM S1 in Fig. 3. Then
the c-to-v messages can be recovered from the sorting results
using Path Constructor-I, which consists of copies of the
architecture in Fig. 4. For QCNB-LDPC codes, each column of
has at most one nonzero entry in each layer. Denote the v-to-c
LLRs of layer in the th decoding iteration by . Represent
the c-to-v LLRs computed from layer in the th iteration by
. It can be derived that [14]