aligned at the PLL due to local feedback. This
aligned_A
signal
is effectively the output of a digital phase detector, its period-
icity re
fl
ecting the common base period of the reference clock.
Aligned_A
is then used to track the CMP tree latency using
delayed clocking to arrive at the Clock Control Unit (CCU)
boundary as
Aligned_B
. Thus,
Aligned_A
is synchronous to
cmp_pll_clk whereas
Algined_B
is synchronous to l2clk no
matter what the balanced CMP latency. This is a cheaper
alternative than having the PLL reference clock being sent
out side by side along with the CMP clock.
Aligned_A
has
one other function of generating a synchronous reset for the