The anticipated advent of practical nanoscale
technology sometime in the next decade with likely
experimental technologies nearer term presents
enormous opportunities for the realization of future
high performance computing potentially in the pan-
Exaflops performance domain (1018 to 1021 flops),
but imposes substantial, albeit exciting, technical
challenges as well. With device density (basic
components per unit area) at nanoscale predicted at
least 1000X today’s commercial feature size and
local clock rates expected to be at least 10X that of
current generation semiconductor technology,
advanced technologies will perform in an operational
regime dramatically different from conventional
CMOS-based microprocessors and DRAM at present.