An electronic equivalent for the transmission of computer transistor-transistor-logic
(TTL) information is provided in Fig. 7.71a. With the Enable control in the “on” or l-state,
the TTL information at the input to the AND gate can pass through to the gate of the JFET
configuration. The design is such that the discrete levels of voltage associated with the
TTL logic will turn the JFET on and off (perhaps 0 V and -5 V, respectively, for a JFET
with VP = -4 V). The resulting change in current levels will result in two distinct levels
of light intensity from the LED (Section 1.16) in the drain circuit. That emitted light will
then be directed through the cable to the receiving station, where a photodiode (Section
16.6) will react to the incident light and permit different levels of current to pass through
as established by V and R. The current for photodiodes is a reverse current having the direction shown in Fig. 7.7la, but in the ac equivalent the photodiode and the resistor R are
in parallel as shown in Fig. 7.'71b, establishing the desired signal with the polarity shown
at the gate of the JFET. Capacitor C is simply an open circuit to dc to isolate the biasing
arrangement for the photodiode from the JFET and a short circuit as shown for the signal
vs. The incoming signal will then be amplified and will appear at the drain terminal of the
output IFET.