The sign change is the result of trigonometrical algebra. Linearity in this phase detector
is preserved for ’5128, otherwise an inverse sine nonlinearity must be used to recover
a voltage proportional to ’.
A NAND gate flip-flop (FF) phase detector, which works with TTL signals is shown in
Figure 8.54A. The input analog sine waves are converted to TTL square waves by
amplitude comparators connected as zero crossing detectors with hysterisis for noise
rejection. The TTL square wave outputs from the comparators are further conditioned
by one-shot multivibrators such as 74LS123s, which have narrow complimentary outputs
with dwell times generally much less than T/100. A simple NAND gate R-S flip-flop
produces an output whose duty cycle depends on the phase difference between the input
signals. As seen from the waveforms of Figure 8.54B, the FF output has a 50% duty
cycle when ’ is 180. The FF output, Z(t), is inverted and averaged by the op-amp low
pass filter and the dc level is adjusted so that, when ’ 1⁄4 1808, the op-amp output voltage,
Z, is zero. A plot of Z vs ’ is shown in Figure 8.54C; note that it is periodic.
An exclusive NOR gate can also be used for an analog phase detector. The input signals
are converted to TTL square waves for input to the ENOR gate; the gate’s output
is a double frequency TTL pulse train whose duty cycle varies linearly with ’. As in
the case of the RSFF phase detector, the ENOR’s output, W(t), is averaged by low-
pass filtering and the dc level is adjusted. The dc op-amp output, W, is also a periodic
function of ’.
A third, logic based phase detector IC utilizes NAND gates. Figure 8.55A illustrates
the simplified innards of the Motorola MC4044 phase detector and shows how its two
outputs can be connected to an op-amp circuit which does low-pass filtering and dc
Basic Electrical Measurements