For the collector-feedback biased npn transis circuit in Figure 16-1, the dc load line crosses the horizontal axis on the collector characteristic curve plot at a value of collector-emitter voltage (Vce) equal to Vcc (Ic=0). It crosses the vertical axis ata value of collector curret(Ic) equal to Vcc/Rc (Vce=0).
The operating(Q-point) is located on the dc load line. It is determined from the value of the collector current (Ic). For maximum operating point stability with collector feedback bias, the value of the base resistor (Rb) must be much greater than βdc Rc. In order for the operating point to be close to the middle of the load line with collector-feedback bias, the value of the base resistor (Rb) must be approximately equal to βdc Rc. Therefore, keeping the operating point close to the center of the load line requires some sacrifice in operating point stability.
The dc current gain (βdc) is calculated by dividing the dc collector current (Ic) by the dc base current(Ib) thereforn, neglecting leakage current,
βDC=
The collector-emitter voltage (vce) for the collector-feedback biased npn transistor circuit is calculated from Kirchoff’s voltage law. Therefore,
Vcc=(Ic+Ib)Rc+Vce=IcRc+Vce
And
Vce=Vcc- IcRc
Collector-feedback bias is one of the simplest biasing networks, but the operating point is not as stable as with some of the other biasing configurations if it is desired to keep the operating point in the center of the load lind.