START and STOP Conditions
Within the procedure of the I2C bus, unique situations
arise which are defined as START (S) and STOP (P)
conditions.
START: A HIGH to LOW transition on the SDA line
while SCL is HIGH
STOP: A LOW to HIGH transition on the SDA line
while SCL is HIGH
The master always generates START and STOP
conditions. The bus is considered to be busy after the
START condition. The bus is considered to be free
again a certain time after the STOP condition. The bus
stays busy if a repeated START (Sr) is generated
instead of a STOP condition. In this respect, the
START (S) and repeated START (Sr) conditions are
functionally identical. The S symbol will be used as a
generic term to represent both the START and repeated
START conditions, unless Sr is particularly relevant.
Detection of START and STOP conditions by devices
connected to the bus is easy if they incorporate the
necessaryinterfacinghardware.However,
microcontrollers with no such interface have to sample
the SDA line at least twice per clock period to sense the
transition.
HARDWARE CONFIGURATION
Slide 33 shows the hardware configuration of the I2C
bus. The ‘bus’ wires are named SDA (serial data) and
SCL (serial clock). These two bus wires have the same
configuration. They are pulled-up to the logic ‘high’
level by resistors connected to a single positive supply,
usually +3.3 V or +5 V but designers are now moving
to +2.5 V and towards 1.8 V in the near future.
All the connected devices have open-collector (open-
drain for CMOS - both terms mean only the lower
transistor is included) driver stages that can transmit
data by pulling the bus low, and high impedance sense
amplifiers that monitor the bus voltage to receive data.
Unless devices are communicating by turning on the
lower transistor to pull the bus low, both bus lines
remain ‘high’. To initiate communication a chip pulls
the SDA line low. It then has the responsibility to drive
the SCL line with clock pulses, until it has finished, and
is called the bus ‘master’.
BUS COMMUNICATION
Communication is established and 8-bit bytes are
exchanged, each one being acknowledged using a 9th
data bit generated by the receiving party, until the data
transfer is complete. The bus is made free for use by
other ICs when the ‘master’ releases the SDA line
during a time when SCL is high. Apart from the two
special exceptions of start and stop, no device is
allowed to change the state of the SDA bus line unless
the SCL line is low.
If two masters try to start a communication at the same
time, arbitration is performed to determine a “winner”
(the master that keeps control of the bus and continue
the transmission) and a “loser” (the master that must
abort its transmission). The two masters can even
generate a few cycles of the clock and data that
‘match’, but eventually one will output a ‘low’ when
the other tries for a ‘high’. The ‘low’ wins, so the