In our mixed-cell cache architecture, we allocate write misses only to robust ways, and read misses to non-robust ways. On a read miss, we choose a replacement victim, NR_LRU, only from non-robust ways based on LRU bits. On a write miss, we choose a victim, GLOBAL_LRU that is the LRU line among all ways of the set (both robust and non-robust). If the victim line is robust, we trigger a writeback for modified data, and allocate the new line in its place. If the chosen victim is in a non-robust way, we choose the LRU line from the two robust ways (RB_LRU), trigger a writeback for modified data to convert the RB_LRU line to a clean line, move the RB_LRU line to use the GLOBAL_LRU line’s storage, and allocate the new line to the RB_LRU line.