those situations, the improvement over communication latency
is still significant. The results also show that the performance
improvement is higher with more bus segments. But increasing
the number of bus segments may lead to more interconnection
and longer arbitration delay. Therefore, a tradeoff between the
performance and hardware cost should be considered.
Another set of experiments are performed to examine the
impact on the bus performance due to the delay of second leve
arbitration. We assume that the arbitration latency is increased
by one due to the second level arbitration. Fig. 7 shows the per
formance of split buses with six bus segments under uniform
Poisson and exponential communication distance distribution
For comparison purpose, the performance of traditional bus ar
chitecture with zero arbitration latency are also shown. Only
one set of results is shown for traditional bus architecture be
cause the communication distance distribution does not affect
the performance of traditional buses. The results show that the
split buses can still have significant better performance in most
cases. Only when the bus traffic is extremely low can the tra
ditional buses outperform split buses marginally. For designs
with high communication requirement, which is typical of cur
rent and future SoC, the split bus architecture would be more
suitable.