Chapter 2
Introduction
STM32 F1
The STM32 F1xx micro-controllers are based upon the A CortexM3 core. The Cortex-M3 is also the basis for micro-controllers from a number of other manufacturers including TI, NXP, Toshiba, and Atmel.
Sharing a common core means that the software development tools including compiler and debugger are common across a wide range of micro-controllers.
The Cortex-M3 differs from previous generations of ARM processors by defining a number of key peripherals as part of the core architecture including interrupt controller, system timer, and debug and trace hardware (including external interfaces).
This additional level of integration means that system software such as real-time operating systems and hardware development tools such as debugger interfaces can be common across the family of processors.
The various Cortex-M3 based micro-controller families differ significantly in terms of hardware peripherals and memory – the STM32 family peripherals are completely different architecturally from the NXP family peripherals even where they have similar functionality.
In this chapter we introduce key aspects of the Cortex-M3 core and of the STM32 F1xx micro-controllers.
A block diagram of the STM32F100 processor used on the value line discovery board is illustrated in Figure 2.1.
The Cortex-M3 CPU is shown in the upper left corner. The value line components have a maximum frequency of 24 MHz – other STM32 processors can support a 72 MHz clock.
The bulk of the figure illustrates the peripherals and their interconnection. The discovery processor has 8K bytes of SRAM and 128K bytes of flash.
There are two peripheral communication buses – APB2 and APB1 supporting a wide variety of peripherals.