3 THE TSBCS/BS ARCHITECTURE
3.1 High-Level Architecture
As shown in Fig. 2, our proposed switch architecture contains
three stages of buffered switch modules, called input
modules (IMs), central modules (CMs) and output modules
(OMs), respectively. Each IM has n input links, each connecting
to an ingress line card (ILC), and n output links,
each connected to a different CM. Each CM has n input
links from n different IMs and n output links to every OM.
Each OM includes n input links from different CMs and
n output links connecting to n egress line cards (ELCs). As a
result, these switch modules are connected as a rearrangeable
non-blocking, three-stage buffered Clos network. The
buffers in each IM are organized into n virtual output-module
queues (VOMQs), each storing the cells destined for a
corresponding OM. For example, all the cells in VOMQk;l
are from the input ports within IMk and are destined for
any output port of OMl. The CMs are buffered crossbars.
Each crosspoint queue (CQ) stores cells from a specific IM
and destined for a distinct OM. For example, CQm;k;l in
CMm contains all the cells from IMk and destined for OMl.
The buffers in each OM are arranged into n output queues,
each storing all the cells destined for an output port. As a
result, the total number of input/output ports is N =n2. In
the rest of this paper, we always consider n=รากที่2ของN