It is known that suppose the delay time
and/or the sequence of transmission for each submodule circuit
is different, then unstable output signal and/or unexpected
results may occur. The latch circuit is in fact set up at the ends
of fuzzification, DML, and defuzzification submodules. Its
objective is that the input signals of the present stage will not
vary with the outputs changes of the former stage submodule.
The implementation of the digital FLC module is shown in
Fig. 10(g), where all the submodules and the pipeline data latch
architecture are included.