For optimum performance, the 4LOx inputs are driven differ-entially but can also be driven in a single-ended fashion. A good choice for a drive is an LVDS device. The common-mode range on each pin is approximately 0.2 V to 3.8 V with nominal ±5 V supplies.
The minimum LO level is frequency dependent (see Figure 22). For optimum noise performance, it is important to ensure that the LO source has very low phase noise (jitter) and adequate input level to ensure stable mixer-core switching. The gain through the divider determines the LO signal level vs. RF frequency. The AD8333 can be operated to very low frequencies at the LO inputs if a square wave is used to drive the LO.
Beamforming applications require a precise channel-to-channel phase relationship for coherence among multiple channels. A reset pin (RSET) is provided to synchronize the 4LOx divider circuits when AD8333s are used in arrays. The RSET pin resets the counters to a known state after power is applied to multiple AD8333s. A logic input must be provided to the RSET pin when using more than one AD8333. See the Reset Input section for more details.