The signal graph window also displays the
timing diagrams of the CPU, memory, DMA,
KP1, and KP2 clocks when the simulation
stops. The first vertical line points to the system
parts where the clocks occurred, while the
next two lines point to where the next two
clocks will occur.
The status window at the very bottom of
the screen shows several key parameters:
what the block diagram window shows, the
parts of the system where the clocks
occurred, and the total number of elapsed
system clocks.