In a write invalidate protocol, when processor A writes in its cache (for location 1000) it broadcasts the information to all other processors through the bus. All processors who have mapped the location 1000 in their cache mark it invalid. Subsequently, if another processor accesses 1000 again, it results in a cache miss and the following action take place:
(a) In the case of a write-through cache, the entry should have been already updated
(b) In the case of a write-back Cache, processor A must detect the read request by another processor, and supply the latest value.
Fig 12.27(a) and (b) display the pins relevant to the cache invalidation in 80486 and Pentium processors.