2.2 Wiring cost function The total wiring cost for a give floorplan is designed as
*****************************(3)
Where Dij is the Manhattan distance between modules i and j in a chip. Total of working area is
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Where n is the number of modules. The floorplan is rearranged for the smallest wiring cost by fixing total width (Wr) of each row and adjusting height (Hr) of each row which are rearranged for wiring length minimization.