be served earlier. Even better, Half-DRAM-2Row has further
performance improvement over all tests. The additional
improvement is from enhanced memory parallelism as expected.
At this time, two requests that go to the Odd and Even
group separately can be served in parallel. In general, 16.9%
performance improvement is observed in Half-DRAM-2Row.
A Case Study of Half-DRAM So far, it is clear that the
performance advantage of Half-DRAM is promising in a memory
that suffers from the restricted power constraint. Wide
I/O [9] is such a memory in which the Four-activation-window
is further restricted to Two-activation-window (tTAW) due
to the challenging power delivery issue in 3D-stacked memory
[35, 36]. In other words, in any tTAW there can be only
two activations allowed. Considering the larger window in
Wide I/O memory (tTAW=50ns and tRRD=10ns), the power
constraint more severely suppresses the performance8. We
apply Half-DRAM-2Row to Wide I/O memory to assess the
possible performance gain. Note that all requests still go to
one channel because the Two-activation-window is applied
within each channel. The results are given in Figure 11b. Not
surprisingly, the average performance improvement is up to
38.1% while test3 and test5 gain as much as 52.4% and 49.2%
speedup, respectively. Therefore, Half-DRAM is very effective
in Wide I/O memory to exploit the potential performance
benefit.