Key hardware features
Since the PA-8000’s completely redesigned
core uses no circuitry from previousgeneration
processors, we could design the
new processor with any microarchitectural
features necessary to attain high performance.
Figure 1 (next page) shows a functional-block
diagram of the PA-8000’s basic control and
data paths.
The chip’s most notable feature is the 56-
entry instruction reorder buffer, to our
knowledge the industry’s largest, which
serves as the central control unit. It supports
full register renaming for all instructions in
the buffer and tracks instruction interdependencies
to allow dataflow execution
through the entire 56-instruction window.