I. INTRODUCTION
The traditional approach to develop a digital system was
to use a set of interconnected digital integrated circuits like
counters, buffers, logic gates and memory. That task required
lots of analysis, testing and the need to adapt the design to
the hardware’s inherent limitations (speed, response time,
power consumption, etc.) which resulted in capped
headroom for development.
Also, every design change implied a whole analysis but
sometimes the prototyping hardware wouldn’t allow any
expansion without a considerable –and most times
expensive- upgrade.
A the present time, technological advance has brought
new options like programmable logic as Complex
Programmable Logic Devices (CPLD) or Field
Programmable Gate Arrays (FPGA) with more sophisticated
simulation and design verification environments, which
enable engineers to reach new levels of complexity and
robustness, while greatly reducing the time between
development and implementation.
Also, those advances let engineers focus on the
application needs, rather than to fit the system onto existing
hardware. This way, one can develop a system that can be
optimized for manufacturing on a single chip, with the
capacity to add or remove modules according to the
requirements in the future.
Modern processor design sometimes reduce the
implementation effort by acquiring some of these elements
as Intellectual Property (IP) or through implementation
techniques to build the other components, like VHDL or
Verilog language and a proprietary synthesizer depending on
each hardware vendor.
There exist different approaches in order to obtain high
comprehension when explaining computer architecture, one
approach uses simulation of processors that allow interaction
with each module that composes a computer as on [1]-[4];
another option is to use FPGA devices and VHDL language
to construct a simple computer [5]-[6], but there is the
disadvantage that by programming there is a lack of
understanding in dataflow. There is even an approach that
uses MSI digital components such as TTL in order to
construct a computer [7], it is a good exercise to realize
interconnections between components, but sometimes using
wires to build those connections is excessively timeconsuming.
On the other hand, there is an option to construct a simple
computer by using a GUI that allow to design at gate level by
placing components in a spreadsheet, it is easy to use and
easy to understand dataflow between components even is
more comprehensive if we can create all of the computer
components from logical gates.
In the present work, the design of an 8-bit data width
Reduced Instruction Set Computer (RISC) processor is
presented; it was developed with simplicity and
implementation efficiency in mind. It has a complete
instruction set, program and data memories, general purpose
registers and a simple Arithmetical Logical Unit (ALU) for
basic operations. It operates following a multi-cycle
execution nature and is implemented on a Xilinx Spartan-3E
FPGA.
In the following section the main characteristics of
presented processor are presented. The third section
introduces the instruction set and its instruction format used
to interact through a programming language with the
processor. Fourth section presents the different blocks that
constitute the processor and its integration. On section five,
timing and implementation results are presented followed by
conclusions at sixth section.
II. CPU ARQUITECTURE
The processor is based on the Harvard architecture, in
which the size of the instructions is not related to the size of
the data, and therefore it can be optimized in a way that any
instruction occupies a single position of program memory,
thus obtaining greater speed and a minor program length.
Also, the access time to the instructions can be superposed
with the one of the data, obtaining a greater speed in each
operation.
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978-1-61284-840-2/11/$26.00 ©2011 IEEE