The storage register
transfers data to the output buffer when shiftregister
clear (SRCLR
)
is high. When SRCLR
is
low,
the input shift register is cleared. When output
enable
(G
)
is held high, all data in the output
buffers
is held low and all drain outputs are off.
When
G
is held low,
data from the storage register
is
transparent to the
output buffers.