3. The next four entries in Table 8-1 are simply those for an ordinary negative-edge-triggered JK flip-flop.
SELF-TEST
12. What is the primary difference between a JK and an RS flip-flop?
13. How could you change an edge-triggered RS flip-flop into an edge-triggered JK flip-flop?
8-6 FLIP-FLOP TIMING
Diodes and transistors cannot switch states immediately. It always takes a small amount of time to turn a diode on or off. Likewise, it takes time for a transistor to switch from saturation to cutoff, and vice versa. For bipolar diodes and transistors, the switching time is in the nanosecond region.
Switching time is the main cause of propagation delay, designated tp. This represents the amount of time it takes for the output of a gate or flip-flop to change states after the input changes. For instance, if the data sheet of an edge-triggered D flip-flop lists tp = 10 ns, it takes about 10 ns for Q to change states after D has been sampled by the clock edge. This propagation delay time has been used to construct the “pulse-forming circuit” used with edge-triggered flip-flop. When flip-flops are used to construct counters, the propagation delay is often small enough to be ignored.
Stray capacitance at the D input (plus other factors) makes it necessary for data bit D to be at the input before the clock edge arrives. The setup time tsetup is the minimum amount of time that the data bit must be present before the clock edge hits. For instance, if