Ultralow-voltage design challenges.Aggressive voltage scaling into sub-Vt requires special circuit topologies and design methodologies to address two fundamental challenges: Vt variation and degraded ION/IOFF. With the extremely fine device dimensions of advanced technologies, a countable number of atoms interact to set the device parameters, and small fluctuations, known as random dopant fluctuation (RDF) (68), and process-control limitations prominently affect Vt. Consequently, ID, due to its exponential dependence on Vt (see Equation 2), varies overwhelmingly, prohibiting circuit topologies that rely on relative device strengths. Additionally, because the absolute currents are low in sub-Vt, the ION/IOFF ratio is degraded by three to five orders of magnitude compared with nominal supply voltages. As a result, the interaction between both “on” and nominally “off” devices becomes important in setting node voltages.