The access transistor injects current into
the storage material and thermally induces
phase change, which is detected during
reads. The chalcogenide’s resistivity captures
logical data values. A high, short current
pulse (reset) increases resistivity by abruptly
discontinuing current, quickly quenching
heat generation, and freezing the chalcogenide
into an amorphous state. A moderate,
long current pulse (set) reduces resistivity by
ramping down current, gradually cooling
the chalcogenide, and inducing crystal
growth. Set latency, which requires longer
current pulses, determines write performance.
Reset energy, which requires higher
current pulses, determines write power.
Cells that store multiple resistance levels
could be implemented by leveraging intermediate
states, in which the chalcogenide is partially
crystalline and partially amorphous.9,11
Smaller current slopes (slow ramp-down)
produce lower resistances, and larger slopes
[3B2] mmi2010010131.3d 1/2/010 17:17 Page 132
(a) (b)
Bitline
Storage
Wordline
Access device
Chalcogenide
Metal (access)
Heater
Metal (bitline)
Figure 1. Storage element with heater and chalcogenide between
electrodes (a), and cell structure with storage element and bipolar junction
transistor (BJT) access device (b).
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132 IEEE MICRO
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(fast ramp-down) produce higher resistances.
Varying slopes induce partial phase transitions
and/or change the size and shape of
the amorphous material produced at the
contact area, generating resistances between
those observed from fully amorphous or
fully crystalline chalcogenides. The difficulty
and high-latency cost of differentiating between
many resistances could constrain
such multilevel cells to a few bits per cell.