shows the speedup of different alternatives described in Section 5.3 compared to the ROBUST mechanism (where all the cells are robust, and the cache size is smaller than the baseline). The write-through (WT) mechanism performs 18% worse, on average, due to additional writeback traffic that increases congestion in the on-die interconnect and memory bus. The MC_DISABLE proposal in [7] has the whole cache operational at the single-processor, high-voltage configuration, so it performs 9.5% better than ROBUST. Our MC mechanisms perform similar to MC_DISABLE if we use LRU cache replacement at high voltage. However, if we use the same replacement policy as low-voltage (Section 3.2), they perform better by 5.6% (MC_WB), 8.4% (MC_SWP), and 3.4% (MC_DUP) on average.